1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device having a metal wiring layer, such as a copper layer, surrounded by insulating films.
2. Description of the Related Art
A wiring layer in a semiconductor device is usually made of copper (Cu). However, since copper has a rapid oxidation rate, a copper wiring layer has problems, when an insulating film is formed on a copper wiring layer, that a copper wiring layer is oxidized at a surface thereof, and that copper is diffused into an insulating film with the result of an increase of a wiring resistance and wiring leakage. In order to solve those problems associated with a copper wiring layer, there has been suggested a structure for enhancing oxidation resistance in films surrounding a copper wiring layer, and a method of fabricating the structure by T. Takewaki in an article entitled "Cu Interconnect Technology for Subquarter-micron ULSIs", Electronic Data Communication Academy Electronics Society Conference, 1995, C-418, pp. 115-116.
The suggested method is illustrated in FIGS. 1A and 1B. First, as illustrated in FIG. 1A, a silicon dioxide film 104a is formed on a silicon substrate 101. Then, a wiring layer formed of a Cu film 107a is formed on the silicon dioxide film 104a. Then, as illustrated in FIG. 1B, the silicon substrate 101 is exposed to mono-silane (SiH.sub.4) gas 109c while being heated, to thereby react copper contained in the Cu film 107a with Si contained in the mono-silane (SiH.sub.4) gas. As a result, there is formed a CuxSiy layer or a Cu silicide layer 107c around the Cu film 107a. Herein, x and y indicates positive integers. The thus formed Cu suicide layer 107c prevents oxidation of the Cu film 107a.
In order to prevent oxidation of copper which occurs when an interlayer insulating film is formed on a copper wiring layer, there has been also suggested a method by H. Miyazaki in an article entitled "The fabrication of double-level copper interconnection using dry etching", Electronic Data Communication Academy Electronics Society Conference, 1995, C-419, pp. 117-118. The suggested method is illustrated in FIGS. 2A and 2B.
First, a BPSG film 104c is formed on a silicon substrate 101, and then a first tungsten (W) film 106d, a copper film 107a, and a second tungsten film 106e are formed on the BPSG film 104c in this order. Then, those films 106e, 107a and 106d are successively etched with an insulating film (not illustrated) used as a mask by high-temperature reactive ion etching, employing a mixture gas of silicon tetrachloride (SiCl.sub.4), nitrogen (N.sub.2) and oxygen (O.sub.2) as an etching gas. Thus, as illustrated in FIG. 2A, a copper wiring layer 107 consisting of the multilayered tungsten film 106e, copper film 107a and tungsten film 106d is formed on the BPSG film 104c. Then, as illustrated in FIG. 2B, a silicon dioxide film or plasma-enhanced TEOS oxide film (PE-TEOS oxide film) 108d is formed so as to entirely cover the copper wiring layer 107 therewith by plasma-enhanced chemical vapor deposition (PE-CVD) where a mixture gas of tetra ethoxy silane (TEOS) and oxygen (O.sub.2) is employed.
In the above-mentioned high-temperature reactive ion etching, a protection film (not illustrated) made of silicon dioxide or similar material is formed on a sidewall of the copper wiring layer 107. According to Miyazaki, the thus formed protection film and TEOS cause copper oxidation rate to be very slow, and accordingly, oxidation of copper which occurs when an insulating film is formed does not cause a practical problem.
Japanese Unexamined Patent Publication No. 3-289156 has suggested a method of providing an ability of preventing copper diffusion with an insulating film to be formed on a copper wiring layer. The method is illustrated in FIGS. 3A to 3D. First, as illustrated in FIG. 3A, there are formed field oxide films 102 at a surface of a p-type silicon substrate 101 by selective oxidation. Then, an n-type diffusion layer 103 is formed between the field oxide films 102 by ion-implantation. Then, a boron-phosphorus glass (BPSG) film 104c having a thickness of 300 nm and containing boron at 1.0 mol % and phosphorus at 4.0 mol % is formed entirely over the substrate 101, followed by annealing at 850.degree. C. for 20 minutes in nitrogen atmosphere. Then, an interconnection contact hole 105b is open throughout the BPSG film 104c so that the n-type diffusion layer 103 appears.
Then, as illustrated in FIG. 3B, a titanium nitride (TiN) film 106a and a copper (Cu) film 107a are formed by sputtering over the product of FIG. 3A. The TiN film 106a has a thickness of 100 nm, and the Cu film 107a has a thickness of 500 nm. Then, the films 106a and 107a are dry-etched using BCl.sub.3 gas to thereby form a patterned Cu/TiN wiring layer.
Then, as illustrated in FIG. 3C, a PSG film 108b having a thickness of 1000 nm and containing phosphorus at 1.2 mol % is formed over the produce of FIG. 3B by chemical vapor deposition (CVD). Then, an interconnection contact hole 105c is formed throughout the PSG film 108b.
Then, as illustrated in FIG. 3D, a 100 nm thick TiN film 106c and a 500 nm thick Cu film 107b are formed over the product of FIG. 3C by sputtering, followed by dry etching, using BCl.sub.3 gas, to thereby form a Cu/TiN wiring layer. Then, there is formed as an uppermost layer a PSG film 108c having a thickness of 1000 nm and containing phosphorus at 1.2 mol %.
The inventor measured a leak current at pn junction between the n-type diffusion layer 103 and the p-type silicon substrate 101. The result was that the same performance as that of an Al-Si electrode was obtained. According to the Publication, one of the following films may be employed in place of the PSG film 108c:
(a) a SiO.sub.2 film formed by sputtering, PA1 (b) a SiO.sub.2 film formed by plasma-enhanced CVD, or PA1 (c) a multi-layered structure comprising silicone resin formed by either phosphorus ion implantation into SiN or SiON, or annealing in POCl.sub.3 atmosphere, and a SiO.sub.2 film containing no phosphorus. PA1 Source gas: triethoxyfluorosilane (FSi(OC.sub.2 H.sub.5).sub.3)+O.sub.2 PA1 Pressure: 10 Torr PA1 Substrate Temperature: 50.degree. C.
Japanese Unexamined Patent Publication No. 7-176612 has suggested a semiconductor device and a method of fabricating the same for the purpose of prevention of oxidation at a surface of a copper wiring layer, prevention of an increase in connection resistance, and higher speed operation of a circuit. FIGS. 4A to 4C illustrate steps of the suggested method.
First, as illustrated in FIG. 4A, an about 500 nm thick silicon dioxide film 104a is formed on a silicon substrate 101. Then, there are deposited a 50 nm thick Ti film 106f, a 100 nm thick TiN film 106a, and an about 800 nm thick Cu film 107a on the silicon dioxide film 104a in this order by sputtering. Then, the thus deposited Ti, TiN and Cu films 106f, 106a and 104a are etched in a conventional manner to thereby form a wiring layer 107.
Then, as illustrated in FIG. 4B, a fluorine (F) containing silicon dioxide film 108e having a thickness of about 500 nm is formed over the wiring layer 107 and the silicon dioxide film 104a by plasma-enhanced CVD. The conditions for plasma-enhanced CVD are as follows.
After application of silanol solution over the fluorine containing silicon dioxide film 108e, an about 300 nm thick fluorine containing spin-on-glass film 110c is formed on the fluorine containing silicon dioxide film 108e by evaporation of triethoxyfluorosilane.
Then, as illustrated in FIG. 4C, a second fluorine containing silicon dioxide film 110d is formed entirely over the spin-on-glass film 110c. The second fluorine containing silicon dioxide film 110d is about 400 nm thick. Then, interconnection contact holes are formed so that the wiring layer 107 appears. Then, a second wiring layer comprising a Ti film 106g, a TiN film 106c and a Cu film 107b is formed within the interconnection contact holes in the same way as that of the wiring layer 107.
In accordance with the above-mentioned method, the fluorine containing silicon dioxide film 108e as an insulating film is formed on the Cu film 107a at a temperature lower than a temperature at which copper is oxidized. In addition, the fluorine containing silicon dioxide film 108e has a lower dielectric constant than that of a silicon dioxide film. Hence, it is possible to obtain a high fabrication yield and preferred electric performance.
Japanese Unexamined Patent Publication No. 7-176612 has also suggested a method of protecting a copper wiring layer by forming a titanium containing tungsten film (hereinafter, referred to simply as "Ti--W film") on a sidewall of a copper wiring layer, and a method of forming an about 900 nm thick, fluorine containing silicon dioxide film only in a gap of a copper wiring layer at 35.degree. C. which is lower than a temperature at which Cu is oxidized, by liquid deposition wherein oversaturated hydrosilicofluoric acid is employed.
Japanese Unexamined Patent Publication No. 63-299250 has suggested a method of protecting a surface of a copper wiring layer. The suggested method is illustrated in FIGS. 5A to 5C. First, as illustrated in FIG. 5A, a silicon dioxide film 104a is formed on a silicon substrate 101. Then, there are successively formed a Ti film 106f, a TiN film 106a, and a Cu film 107a in this order on the silicon dioxide film 104a. Then, only the Cu film 107a is patterned. Then, the TiN film 106a and the Ti film 106f are patterned with the patterned Cu film 107a being used as a mask. Thus, there is formed a copper wiring layer 107, as illustrated in FIG. 5A.
Then, as illustrated in FIG. 5B, a silicon film 109d is deposited entirely over the copper wiring layer 107 and the silicon dioxide film 104a at a thickness in the range of 10 nm to 50 nm.
Then, the product of FIG. 5B is annealed at 800.degree. C. to 1000.degree. C. in oxygen atmosphere. As a result, silicon contained a portion of the silicon film 109d making contact with the Cu film 107a is diffused into the Cu film 107a to thereby make Cu-Si alloy. In addition, the Cu-Si alloy absorbs oxygen contained in the oxygen atmosphere to thereby make Cu-SiO.sub.2 alloy 107d. That is, SiO.sub.2 penetrates grain boundary of Cu, which ensures prevention of oxidation of copper present in the Cu film 107a. A portion of the silicon film 109d making no contact with the Cu film 107a is oxidized by oxygen contained in the oxygen atmosphere, and is turned into a silicon dioxide film.
In accordance with the method illustrated in FIGS. 3A and 3B, the Cu silicide film 107c is formed around the Cu film 107a, which ensures enhancement in oxidation resistance, corrosion resistance and electro-migration resistance of the Cu film 107a. In addition, since a silicon nitride film is used as an interlayer insulating film, capacity between layers is not increased.
A wiring resistance of the Cu film 107a is dependent on specific surface area thereof against a total surface area of the Cu suicide film 107c having a high resistance. Accordingly, as the Cu film 107a is reduced in size, a ratio of a total surface area to a volume thereof is increased. This means that a smaller wiring layer in size has a higher increasing rate in a wiring resistance. A semiconductor device having a higher increasing rate in a wiring resistance inevitably has greater reduction in performance. This eliminates a merit of forming a wiring layer of copper having a low resistance.
In addition, since copper reacts rapidly with silane (SiH.sub.4), it is not ready to control the reaction between Cu and SiH.sub.4. Hence, it is also difficult to control a thickness of the Cu silicide film 107c, resulting in that it is difficult to obtain a uniform wiring resistance in a wafer or in a lot. This causes a problem that stable electric performance is not ensured in a semiconductor device.
In the method illustrated in FIGS. 2A and 2B, since a protection film made of silicon dioxide or similar material is formed on a sidewall of the copper wiring layer 107 when the copper wiring layer 107 is etched, and the silicon dioxide film 108d is formed on the copper wiring layer 107 employing TEOS source, it is possible to prevent oxidation of copper oxidation which would usually occur when an insulating film is formed on a copper wiring layer, and a wiring resistance is scarcely increased. In addition, a circuit delay caused by an increase of interlayer capacity does not occur.
However, the protection film to be formed on a sidewall of the copper wiring layer 107 is formed in non-equilibrium state while the Cu film 107a is being plasma-etched, and hence could have low thermal stability. This means that the ability of the protection film for preventing diffusion of copper is not so high. Furthermore, though the silicon dioxide film 108d formed by plasma-enhanced CVD employing TEOS source gas has a barrier against copper, the barrier is not so high. Accordingly, diffusion and/or oxidation of copper might occur when a plurality of annealing are carried out for fabricating a multi-layered wiring, which causes defectiveness because of current leakage between wirings, and an increase in a wiring resistance. As a result, there is caused a problem that it is quite difficult to have a high fabrication yield and long-term reliability.
The method illustrated in FIGS. 3A to 3B is surely effective for preventing copper diffusion by means of a phosphorus containing insulating film such as the PSG films 108b and 108c. However, a PSG film formed by CVD can have poor step coverage, and hence is not applicable to very fine wiring spaces.
In addition, the formation of an insulating film for prevention of copper diffusion by phosphorus ion implantation into a silicon dioxide film and annealing in POCl.sub.3 atmosphere is accompanied with a major problem in respect of fabrication steps. For instance, it would take much time and much cost to implant phosphorus ion having a mol-order concentration, and it would be necessary to carry out annealing at a high temperature for introducing phosphorus into a silicon dioxide film from POCl.sub.3 atmosphere. The high temperature annealing might exert a harmful influence on a transistor and/or a wiring.
When a multi-layered structure comprising silicone resin containing phosphorus at 4.0 mol % and a silicon dioxide film containing no phosphorus is to be fabricated, there are caused problems in fabrication of a multi-layered wiring and in long-term reliability of a semiconductor device, because silicone resin is inferior to an inorganic insulating film with respect to heat resistance, designability in smaller size, and moisture resistance.
In the method illustrated in FIGS. 4A to 4C, an insulating film having a low dielectric constant is formed at a temperature lower than a temperature at which copper is oxidized, by plasma-enhanced CVD wherein triethoxyfluorosilane (FSi(OC.sub.2 H.sub.5).sub.3) and O.sub.2 gases are used as source, or by evaporation of triethoxyfluorosilane. In accordance with the method, an insulating film can be surely formed without oxidation of copper. However, the thus formed insulating film does not have a barrier performance against copper, and has poor stability because it is formed at a low temperature. Accordingly, there may be caused problems that copper is diffused because of annealing to be carried out after the formation of the insulating film, and that performance of a semiconductor device is deteriorated and long-term reliability to a semiconductor device is reduced both because of absorption of moisture thereinto.
These problems may be solved by a process including steps of covering a sidewall of a wiring layer with a Ti--W film by anisotropic etch-back after deposition of a Ti--W alloy film, and then forming an insulating film. However, this process has a problem that adjacent wirings may be short-circuited in a narrow space between wirings because of residue of a Ti--W film, and as a result, it would be difficult to have a high fabrication yield.
The method illustrated in FIGS. 5A to 5C, wherein a silicon film is deposited on a copper film, and then the product is annealed to thereby form a reaction layer, also has a problem that an annealing temperature is in the range of 800.degree. C. to 1000.degree. C., which is too high, and hence the method is not applicable to the formation of a wiring layer. In addition, since the Cu--SiO.sub.2 layer 107d is formed, it is unavoidable that a wiring resistance is increased, which eliminates a merit that copper having a low electrical resistance is used as a wiring.